搜索资源列表
mult
- 32位浮点乘法器的源代码，用verilog来实现的-32-bit floating point multiplier source code to achieve with verilog
32bit_multiplexer
- 32位高性能浮点乘法器芯片设计研究.pdf-32-bit high-performance floating-point multiplier chip design research. Pdf
csa_float_multiplier
- 新型的浮点乘法器 用csa来实现可以用在浮点乘法器的地方-A new type of floating-point multiplier with CSA to achieve floating-point multiplier can be used in place
JPEG2000_9_7_002.pdf
- 基于实数的二进制表示法，把CDF(Cohen，Daubechies and Feauveau)9／7双正交小波基的提升系数化为二进制，采用简单的移位一加操作代替结构复杂的浮点乘法器，从而实现了JPEG2000中9／7离散小波变换的定点计算．相对于浮点计算法，移位一加操作最大的优点是计算简单，特别易于超大规模集成电路实现，因而使硬件实时处理图像信号成为可能．实验仿真结果表明：在低压缩比的情况下，用移位一加操作重构的图像，其峰值信噪比(PSNR)只比浮点法低0．10 dB，当压缩比增大时，其PSNR
FinalFPMultiplier
- Simple 32 bit Floating point Multiplier
floating_multi
- Floating point multiplier
mult
- floating point multiplier
fpu_v19
- Floating Point Multiplier in VHDL
doublemult
- 设计了一个双精度浮点乘法器。该器件采用改进的BOO TH 算法产生部分积, 用阵列和 树的混合结构实现对部分积的相加, 同时, 还采用了快速的四舍五入算法, 以提高乘法器的性能。把 设计的乘法器分为4 级流水线, 用FPGA 进行了仿真验证, 结果正确 并对FPGA 实现的时序结果 进行了分析。-Designed a double-precision floating-point multiplier. The device uses an improved algorithm fo
ADSP-21262
- High performance 32-bit/40-bit floating-point processor Code compatibility—at assembly level, uses the same instruction set as other SHARC DSPs Single-instruction multiple-data (SIMD) computational architecture— two 32-bit IEEE floating-point
CourseDesign
- 用Verilog实现一位原码浮点数乘法器，按照累加的方式，逐位相乘，再相加。-Verilog realization of an original code with floating point multiplier, in accordance with the cumulative way, bit by bit multiply, then add.
cf_fp_mul_latest.tar
- CF Floating Point Multiplier
floating-point-multiplier
- verilog implementation of the floating point multiplier
code
- this file is the vhdl codes for floating point multiplier.
round_nearest
- this file is vhdl codes for rounding the floating point number to nearest number.it is useful for floating point multiplier.
MULT
- the document used to describe the verilog codes design floating point multiplier in coms design
Floating-Point-Multiplier-in-Verilog
- Floating Point Multiplier in Verilog
floating-point-multiplier
- floating point multiplier in VHDL
floating-point-multip
- verilog code for floating point multiplier
Fixed-Floating-Point-Adder-Multiplier-master
- Fixed-Floating-Point-Adder-Multiplier with test bench